Four-Channels High-Resolution Frequency Counter for QCM Sensor Array Using Generic FPGA XC6SLX9 Board

• Published in: Journal of Electrical and Computer Engineering Vol. 2023; pp. 1 - 10
• Main Authors: Triqadafi, Adin O., Zafirah, Tyas N., Dharmawan, Hari A., Sakti, Setyawan P.
• Format: Journal Article
• Language: English
• Published: New York Hindawi 09.05.2023; John Wiley & Sons, Inc; Hindawi Limited
• Subjects: Circuit design; Circuit printing; Communication; Crystal oscillators; Digital integrated circuits; Electronic noses; Energy consumption; Field programmable gate arrays; Frequency counters; Frequency shift; High resolution; Methods; Microcontrollers; Modules; Multichannel communication; Multiplication; Phase locked loops; Printed circuits; Quartz crystals; Rubidium; Sampling; Sensor arrays; Sensors; Television broadcasting industry; United Kingdom
• ISSN: 2090-0147; 2090-0155
• DOI: 10.1155/2023/5182455

A frequency counter is essential for resonance-based sensors like quartz crystal microbalance. An electronic nose or tongue using a QCM sensor array requires a multichannel frequency counter to detect the frequency shift of the sensors simultaneously. The frequency counter’s resolution, precision, and sampling speed are important factors. Board size, energy consumption, and rapid deployment are also considered in the design. This work shows the development of an independent multichannel frequency counter using a commercial Xilinx Spartan 6 series XC6SLX9 board module and a microcontroller board. Both modules are general-purpose modules; therefore, there is no need for a printed circuit board design, resulting in a quick implementation: the use of FPGA results in a compact size and low energy consumption. The developed counter is designed based on a reciprocal counter utilizing the internal logic block of the FPGA. The FPGA module has a built-in 50 MHz TCXO clock and is the reference clock. The high-resolution timing of the counter is realized by multiplying the 50 MHz clock by 6 to reach 300 MHz. The multiplication utilizes the PLL modules in the FPGA. The high precision and accuracy of the counter are achieved by calibrating the timing clock to a 10 MHz rubidium oscillator. The data communication to the microcontroller is done via the SPI by implementing the SPI protocol in the FPGA. The resource is optimized by utilizing PLL and DSP blocks for the counter. Only 5% registers and 5% LUTs of the FPGA resource are used to build a four-channel frequency counter. The result shows that the counter can measure the frequency of incoming signals with a resolution of 0.033 Hz at 10 MHz with a sampling time of 1 second. The system has been tested to monitor the frequency changes of a QCM sensor array.