Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit func...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 62; no. 1; pp. 171 - 177
Main Authors Hwang, Byeong-Woon, Yang, Ji-Woon, Lee, Seok-Hee
Format Journal Article
LanguageEnglish
Published New York IEEE 01.01.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Analytical models
Compact modeling
Computational modeling
Electric potential
junctionless (JL) transistor
Logic gates
Mathematical model
multigate MOSFET
Numerical models
Transistors
variability
Compact modeling
variability
multigate MOSFET
junctionless (JL) transistor
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Summary:An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2014.2371075