HW/SW codesign techniques for dynamically reconfigurable architectures

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 10; no. 4; pp. 399 - 415
• Main Authors: Noguera, J., Badia, R.M.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.08.2002; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Architecture; Computation; Computer aided design; Computer programs; Computer science; control theory; systems; Design methodology; Discrete event systems; Dynamic scheduling; Dynamical systems; Dynamics; Electronics; Exact sciences and technology; Hardware; Heuristic algorithms; Integrated circuits; Integrated circuits by function (including memories and processors); Partitioning algorithms; Processor scheduling; Reconfigurable architectures; Runtime; Scheduling; Scheduling algorithm; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software; VLSI circuit; Methodology; Codesign; HW/SW codesign; System design; Dynamic scheduling; Scheduling; Dynamical system; Computing; dynamically reconfigurable architectures; Digital system; Experimental result; Algorithm performance; Partitioning; Logic partitioning; Integrated circuit; Reconfigurable architectures; Simulation model; HW/SW partitioning; Discrete event system
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2002.801575

Hardware/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digital-systems design. However, no previous work has been carried out in order to define a HW/SW codesign methodology with dynamic scheduling for run-time reconfigurable architectures. In addition, all previous approaches to reconfigurable computing multicontext scheduling are based on static-scheduling techniques. In this paper, we present three main contributions: 1) a novel HW/SW codesign methodology with dynamic scheduling for discrete event systems using dynamically reconfigurable architectures; 2) a new dynamic approach to reconfigurable computing multicontext scheduling; and 3) a HW/SW partitioning algorithm for dynamically reconfigurable architectures. We have developed a whole codesign framework, where we have applied our methodology and algorithms to the case study of software acceleration. An exhaustive study has been carried out, and the obtained results demonstrate the benefits of our approach.