A NAND Flash Memory Controller for SD/MMC Flash Memory Card

• Published in: IEEE transactions on magnetics Vol. 43; no. 2; pp. 933 - 935
• Main Authors: LIN, Chuan-Sheng, DUNG, Lan-Rong
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.02.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC); Cards; Chips (memory devices); Circuits; CMOS; Control engineering; Control systems; Costs; Cross-disciplinary physics: materials science; rheology; Error correction; Error correction codes; Exact sciences and technology; Flash memory; Flash memory (computers); flash storage systems; Information storage; Magnetism; Materials science; Metal matrix composites; Microprogramming; Multimedia; NAND flash memory controller; nonvolatile memory; Other topics in materials science; Physics; Product introduction; Product life cycle; Production; Semiconductors; Specifications; Systolic arrays; Very large scale integration; Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC); Proceedings; Composite materials; Storage; Recording material; flash storage systems; NAND flash memory controller; Magnetic recording; nonvolatile memory
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/TMAG.2006.888520

In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances