V-W Band CMOS Distributed Step Attenuator With low Phase Imbalance
This letter presents a high power V-W band CMOS distributed step attenuator with a low phase imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the var...
Saved in:
Published in | IEEE microwave and wireless components letters Vol. 24; no. 8; pp. 548 - 550 |
---|---|
Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.08.2014
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | This letter presents a high power V-W band CMOS distributed step attenuator with a low phase imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the varistor. Shunt t-lines under the varistors compensate for the phase imbalance of the attenuation states. The total chip size is 0.38 {\rm mm}^{2} excluding pads. The insertion loss of the attenuator is 5.6-11.2 dB at 50-110 GHz. The return loss is <- 15 dB at 50-110 GHz with the rms phase imbalance of <1.4^{\circ} and the input 1 dB compression point of 17 dBm. |
---|---|
Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1531-1309 1558-1764 |
DOI: | 10.1109/LMWC.2014.2322442 |