A 640-Mb/s 2048-bit programmable LDPC decoder chip

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 3; pp. 684 - 698
• Main Authors: Mansour, M.M., Shanbhag, N.R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Architecture-aware low-density parity-check (AA-LDPC) codes; Chips; Circuit properties; Clocks; CMOS technology; Code standards; Codes; Computer networks; Convergence; Decoders; Design. Technologies. Operation analysis. Testing; Dissipation; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Interleaved codes; iterative decoders; Iterative decoding; LDPC codes; Lookup tables; Low density parity check codes; Messages; Networks; Parity check codes; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Table lookup; Throughput; turbo-decoding message-passing (TDMP) algorithm; VLSI decoder architectures; Tunable circuit; VLSI circuit; Architecture-aware low-density parity-check (AA-LDPC) codes; turbo- decoding message-passing (TDMP) algorithm; Iterative method; Decoding circuit; Turbo code; Clock; Algorithm; Computational complexity; LDPC codes; Look up table; Convergence speed; iterative decoders; Circuit architecture; Coding; Complementary MOS technology; Integrated circuit; Convergence rate; VLSI decoder architectures; Parity check
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.864133

A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.