An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 4; pp. 823 - 830
• Main Authors: Sohn, K., Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Active control; Applied sciences; Autonomous; Chips; Design. Technologies. Operation analysis. Testing; Detection; Detectors; Electronics; Exact sciences and technology; Fluctuations; General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; Integrated circuits by function (including memories and processors); Leak detection; Leakage current; Leakage current monitor; Monitoring; Monitors; Nanotechnology; Noise; on-chip timer; Physics; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; SRAM; Static random access memory; substrate noise; temperature sensor; Temperature sensors; Timing; Uncertainty; Static random access memory; Random access memory; Measurement sensor; Temperature sensor; Leakage current monitor; SRAM; on-chip timer; Low voltage; Current sensor; Power consumption; Integrated circuit testing; Integrated circuit; substrate noise; Leakage current; Standard deviation; Noise temperature; Circuit noise; Nanotechnology
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.870759

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.