3D monolithic integration: Technological challenges and electrical results

• Published in: Microelectronic engineering Vol. 88; no. 4; pp. 331 - 335
• Main Authors: Vinet, M., Batude, P., Tabone, C., Previtali, B., LeRoyer, C., Pouydebasque, A., Clavelier, L., Valentian, A., Thomas, O., Michaud, S., Sanchez, L., Baud, L., Roman, A., Carron, V., Nemouchi, F., Mazzocchi, V., Grampeix, H., Amara, A., Deleonibus, S., Faynot, O.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Amsterdam Elsevier B.V 01.04.2011; Elsevier
• Subjects: Applied sciences; CMOS; Density; Depletion; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electrostatics; Exact sciences and technology; Germanium; Integrated circuits; Integrated circuits by function (including memories and processors); Intermetallics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicides; Three dimensional; Threshold voltage; Transistor; Transistors; Wafers; CMOS; 3D; Transistor; Germanium; Inverter; Voltage threshold; Static random access memory; Material processing; Random access memory; Depletion layer; Wafer bonding; Crystalline material; Silicon on insulator technology; Microelectronic fabrication; Three dimensional structure; Non volatile memory; Complementary MOS technology; Integrated circuit; Monolithic integrated circuit; Gain; Wafer
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2010.10.022

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650 °C). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.