Spread spectrum clock Generator with delay cell array to reduce electromagnetic interference

• Published in: IEEE transactions on electromagnetic compatibility Vol. 47; no. 4; pp. 908 - 920
• Main Authors: Jonghoon Kim, Dong Gun Kam, Pil Jung Jun, Kim, Joungho
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arrays; Attenuation; Clocks; Delay; Electromagnetic compatibility; Electromagnetic interference; Electromagnetic interference (EMI); Electronics; Exact sciences and technology; Frequency modulation; High speed; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); Interference suppression; Jitter; Phase locked loops; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Spread spectrum; spread spectrum clock (SSC); Spreads; Synchronization; Telecommunications and information theory; GHz range; Performance evaluation; Waveform; Noise reduction; Position control; Electromagnetic compatibility; Clock; Implementation; Phase locked loop; Delay circuit; Electromagnetic interference (EMI); Experimental result; spread spectrum clock (SSC); Electromagnetic interference; Signal generators; System simulation; Spread spectrum; Measurement method; Comparative study
• ISSN: 0018-9375; 1558-187X
• DOI: 10.1109/TEMC.2005.859063

In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz.