Physical Modeling for Programming of TANOS Memories in the Fowler-Nordheim Regime

• Published in: IEEE transactions on electron devices Vol. 56; no. 9; pp. 2008 - 2015
• Main Authors: Compagnoni, C.M., Mauri, A., Amoroso, S.M., Maconi, A., Spinelli, A.S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Devices; Electron traps; Electronics; Exact sciences and technology; Flash memories; Gates; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Mathematical analysis; Mathematical models; Nitrides; Numerical models; Programming; semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solvents; TANOS memories; Transient analysis; Trapping; Tunneling; tunneling program/erase (P/E); Performance evaluation; Charge storage; Oxide layer; Tunnel effect; Transistor gate; Multiple layer; tunneling program/erase (P/E); Erasure; Modeling; Flash memories; Floating gate technology; Semiconductor device; Spatial distribution; Flash memory; semiconductor device modeling; Integrated circuit; TANOS memories; Fowler Nordheim tunneling
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2009.2026315

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.