Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 60; no. 9; pp. 2412 - 2421
• Main Authors: Dong, Guiqiang, Xie, Ningde, Zhang, Tong
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2013; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: BCH codes; Coding; Data transfer; Degradation; Demand; Detection; Entropy coding; Error correction; Error correction codes; Flash memories; Flash memory (computers); Integrated circuit modeling; LDPC; lossless compression; Marketing; NAND flash memory; Parity check codes; Reliability; Sensors; soft sensing; Soft sensors; System-on-chip
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2013.2244361

With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as LDPC codes become very natural alternative options. However, these powerful coding solutions demand soft-decision memory sensing, which results in longer on-chip memory sensing latency and memory-to-controller data transfer latency. Leveraging well-established lossless data compression theories, this paper presents several simple design techniques that can reduce such latency penalty caused by soft-decision ECCs. Their effectiveness have been well demonstrated through extensive simulations, and the results suggest that the latency can be reduced by up to 85.3%.