VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 59; no. 5; pp. 1107 - 1118
• Main Authors: Whatmough, P. N., Perrett, M. R., Isam, S., Darwazeh, I.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; Bandwidth; Bandwidth efficiency; Circuits; Complexity theory; Focusing; Fourier transforms; Frequency division multiplexing; Modulation; multicarrier modulation; OFDM; Spectra; Studies; transmitter; Transmitters; Very large scale integration; wireless communications
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2012.2185304

Spectrally efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the key research challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. Focusing on transmitters, this paper explains the SEFDM concept and examines the complexity of published modulation algorithms, with particular consideration to implementation issues. We then present two new variants of a digital baseband transmitter architecture for SEFDM, based on a modulation algorithm which employs the discrete Fourier transform (DFT) implemented efficiently using the fast Fourier transform (FFT). The algorithm requires multiple FFTs, which can be configured either as parallel transforms, which is optimal for throughput or using a multi-stream FFT architecture, for reduced circuit area. We propose a simplified approach to IFFT pruning for pipeline architectures, based on a token-flow control style, specifically optimized for the SEFDM application. Reconfigurable implementations for different bandwidth compression ratios, including conventional OFDM, are easily derived from the proposed implementations. The SEFDM transmitters have been synthesized, placed and routed in a commercial 32 nm CMOS process technology and also verified in FPGA. We report circuit area and simulated power dissipation figures, which confirm the feasibility of SEFDM transmitters.