A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 20; no. 11; pp. 2044 - 2053
• Main Authors: Kyungho Ryu, Jisu Kim, Jiwan Jung, Jung Pill Kim, Kang, S. H., Seong-Ook Jung
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit properties; Delay; Design optimization; Design. Technologies. Operation analysis. Testing; Detection; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Flip-flops; Integrated circuits; Leakage; Logic; Magnetic and optical mass memories; magnetic tunnel junction (MTJ) logic; Magnetic tunneling; Magnetoelectric, magnetostrictive, magnetoacoustic, magnetooptic and magnetothermal devices. Spintronics; Magnetoelectronics; Memory architecture; nonvolatile flip-flop; retention flip-flop; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Spintronics; spintronics logic; Storage and reproduction of information; Tunnel junctions; Very large scale integration; magnetic tunnel junction (MTJ) logic; Memory devices; spintronics logic; retention flip-flop; Optimal design; nonvolatile flip-flop; Sequential circuit; Magnetic tunneling junction; Flip-flop circuits; Complementary MOS technology; Leakage current; Silicon; Delay time; Compatibility; Spintronics
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2172644

Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention flip-flop. Conventional zero standby leakage retention flip-flops have several problems, including difficulty in design optimization among the C-Q delay, sensing current, and process variation tolerance, and the insufficient write current. In this paper, a new MTJ based retention flip-flop is presented to solve these problems. The proposed retention flip-flop is designed using industry-compatible 45-nm process technology model. The proposed retention flip-flop achieves a 41.58% reduced C-Q delay and a 67.53% lowered sensing current with a 1.06% increased area compared to the previous retention flip-flop.