An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 18; no. 7; pp. 1130 - 1134
• Main Authors: OK, Sunghwa, CHUNG, Kyunghoon, KOO, Jabeom, KIM, Chulwoo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Antiharmonic lock; Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Delay; delay-locked loop (DLL); Design. Technologies. Operation analysis. Testing; Dynamic link libraries; Dynamics; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; false lock; Frequency conversion; Frequency locked loops; frequency multiplication; Frequency multipliers; Integrated circuits; Jitter; limited locking range; Locking; Locks; Phase detection; Phase frequency detector; Power harmonic filters; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Very large scale integration; Voltage control; delay-locked loop (DLL); frequency multiplication; false lock; Frequency scaling; Antiharmonic lock; Jitter; Clock; Combiner circuit; Phase detector; Frequency multiplier; Complementary MOS technology; Frequency converter; Delay time; Delay lock loops; Root mean square value; limited locking range
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2019757

This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm 2 , and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.