Delay-Line-Based Analog-to-Digital Converters

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 6; pp. 464 - 468
• Main Authors: Guansheng Li, Tousi, Y.M., Hassibi, A., Afshari, E.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog-digital conversion; Analog-to-digital converter (ADC); CMOS; CMOS analog integrated circuits; CMOS process; CMOS technology; Converters; Delay effects; delay line; Delay lines; Design engineering; Digital; Electric potential; Flip-flops; Jitter; scaling; Signal resolution; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2009.2020947

We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm 2 ) and small power consumption (<2.4 mW).