Highly Robust Atomic Layer Deposition‐Indium Gallium Zinc Oxide Thin‐Film Transistors with Hybrid Gate Insulator Fabricated via Two‐Step Atomic Layer Process for High‐Density Integrated All‐Oxide Vertical Complementary Metal‐Oxide‐Semiconductor Applications

• Published in: Small structures Vol. 5; no. 2
• Main Authors: Kim, Dong-Gyu, Choi, Su-Hwan, Lee, Won-Bum, Jeong, Gyeong Min, Koh, Jihyun, Lee, Seunghee, Kuh, Bongjin, Park, Jin-Seong
• Format: Journal Article
• Language: English
• Published: Weinheim John Wiley & Sons, Inc 01.02.2024; Wiley-VCH
• Subjects: Aluminum oxide; atomic layer deposition; Atomic layer epitaxy; Gallium; High resistance; hydrogen resistivity; Indium gallium zinc oxide; oxide semiconductors; Robustness; Semiconductor devices; stability; Thin film transistors; Threshold voltage; Transistors; vertical complementary metal-oxide-semiconductor inverter; Voltage gain; Zinc oxide
• ISSN: 2688-4062; 2688-4062
• DOI: 10.1002/sstr.202300375

Highly reliable atomic layer deposition (ALD)‐derived In‐Ga‐Zn‐O thin‐film transistors with high field‐effect mobility (μFE) and hydrogen (H) resistivity are crucial for the semiconductor industry. Herein, a hybrid Al2O3 gate insulator (GI) is proposed that is designed by controlling the plasma‐enhanced ALD and thermal ALD processes in situ to demonstrate robust characteristics. A hybrid GI is applied to the top‐gate geometry of an In0.71Ga0.08Zn0.21O active layer. The optimal device exhibits exceptional electrical characteristics, including a threshold voltage of 0.37 V, μFE of 150.7 cm2 V s−1, subthreshold swing of 64.0 mV decade−1, and hysteresis of 0.02 V. It demonstrates high resistance to H annealing and reliable positive bias temperature stress, as well as changes in VTH shifts of −0.43 and 0.00 V, respectively. The excellent electrical characteristics and high robustness of the device can be attributed to the precise control of H, oxygen, and carbon species within the upper region of the hybrid GI. The achievement of robust device characteristics enables the design of a novel vertical complementary metal‐oxide‐semiconductor inverter that exhibits a voltage gain of 44.7 V V−1 and a noise margin of 87.5% at a 10 V supply voltage. Proposing an atomic layer deposition (ALD)‐derived Al2O3 gate insulator for high‐performance In‐Ga‐Zn‐O thin‐film transistors, this design controls in situ plasma‐enhanced ALD and thermal ALD processes within a top‐gate geometry. The optimal device showcases an exceptionally high mobility of 150.7 cm2 V s−1, robust resistance to hydrogen annealing, and reliable positive bias temperature stress, with threshold voltage shifts of −0.43 and 0.00 V, respectively.