CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

• Published in: IEEE transactions on nanotechnology Vol. 10; no. 2; pp. 217 - 225
• Main Authors: Sheng Lin, Yong-Bin Kim, Lombardi, Fabrizio
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Alternative energy sources; Applied sciences; Arithmetic; Carbon nanotube (CNT) FET (CNTFET); Circuit properties; Circuits; Consumption; Cross-disciplinary physics: materials science; rheology; Delay; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy consumption; Energy efficiency; Exact sciences and technology; Gates (circuits); Integrated circuit interconnections; Logic; Logic circuits; Logic design; Logic gates; Materials science; Molecular electronics, nanoelectronics; multiple-valued logic (MVL) design; Multivalued logic; Nanoscale materials and structures: fabrication and characterization; Nanotubes; Physics; Reduction; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Arithmetic circuit; Nanotube devices; Carbon nanotubes; Multivalued logic; Logic gate; Logic design; Implementation; Nanoelectronics; Carbon nanotube (CNT) FET (CNTFET); multiple-valued logic (MVL) design; Logic circuit; Field effect transistor; Gating circuits; Energy characteristic; Energy dissipation; Interconnection; Energetic efficiency; Summing circuits; Integrated circuit; Resistive load; Electric power consumption; SPICE; Delay time; Multiplying circuits
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2009.2036845

This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.