Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

• Published in: IEEE transactions on device and materials reliability Vol. 8; no. 3; pp. 519 - 525
• Main Authors: Sangwoo Pae, Maiz, J., Prasad, C., Woolery, B.
• Format: Magazine Article
• Language: English
• Published: New York IEEE 01.09.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aging; Bias temperature instability (BTI); Degradation; Devices; Dielectrics; Gates; high- \kappa dielectrics; Instability; metal gate; MOSFETs; Negative bias temperature instability; Niobium base alloys; Niobium compounds; Oxides; Random access memory; Semiconductor device reliability; Semiconductor devices; Semiconductors; SRAM; Titanium compounds; transistor reliability; Transistors; Vccmin
• ISSN: 1530-4388; 1558-2574
• DOI: 10.1109/TDMR.2008.2002351

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the V T variability at both time zero and after NBTI aging increases. The time0 V T variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device Delta V T variability. This paper focuses on the bias temperature instability stress-induced device Delta V T variability and the trend across several technology generations. The remarkable correlation of aging-induced Delta V T variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced Delta V T variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.