Memory characteristics of a self-assembled monolayer of Pt nanoparticles as a charge trapping layer

A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter ∼4 nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO(2)...

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Published inNanotechnology Vol. 19; no. 30; pp. 305704 - 305704 (5)
Main Authors Choi, Hyejung, Choi, Byung-Sang, Kim, Tae-Wook, Jung, Seung-Jae, Chang, Man, Lee, Takhee, Hwang, Hyunsang
Format Journal Article
LanguageEnglish
Published England IOP Publishing 30.07.2008
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Abstract A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter ∼4 nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO(2) substrate using poly(4-vinylpyridine) (P4VP) as a surface modifier. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window of 5.8 V under ± 7 V for program/erase voltage. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices.
AbstractList A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter ∼4 nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO(2) substrate using poly(4-vinylpyridine) (P4VP) as a surface modifier. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window of 5.8 V under ± 7 V for program/erase voltage. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices.
A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter ~4 nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO2 substrate using poly(4-vinylpyridine) (P4VP) as a surface modifier. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window of 5.8 V under +/- 7 V for program/erase voltage. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices.
Author Lee, Takhee
Kim, Tae-Wook
Chang, Man
Choi, Hyejung
Jung, Seung-Jae
Choi, Byung-Sang
Hwang, Hyunsang
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BackLink https://www.ncbi.nlm.nih.gov/pubmed/21828771$$D View this record in MEDLINE/PubMed
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