The LOTTERYBUS on-chip communication architecture

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 14; no. 6; pp. 596 - 608
• Main Authors: Lahiri, K., Raghunathan, A., Lakshminarayana, G.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Allocations; Applied sciences; Architecture; Asynchronous transfer mode; Bandwidth; Bus architecture; Circuit properties; Communication system traffic control; Costs; Delay; Design; Design engineering; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Hardware; Integrated circuits; on-chip communication; Protocols; randomized arbitration; Resource management; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Switches; Switching, multiplexing, switched capacity circuits; System-on-a-chip; System-on-Chip (SoC); Traffic engineering; Traffic flow; Very large scale integration; Performance evaluation; High performance; Bus architecture; on-chip communication; ran domized arbitration; System-on-Chip (SoC); Transmission protocol; Resource sharing; System on a chip; Bus(channel); Implementation; Time division multiple access; Interconnection; Integrated circuit; Subsystem; Selector switch

On-chip communication architectures play an important role in determining the overall performance of System-on-Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In particular, the resource sharing mechanis...