The LOTTERYBUS on-chip communication architecture

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 14; no. 6; pp. 596 - 608
• Main Authors: Lahiri, K., Raghunathan, A., Lakshminarayana, G.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Allocations; Applied sciences; Architecture; Asynchronous transfer mode; Bandwidth; Bus architecture; Circuit properties; Communication system traffic control; Costs; Delay; Design; Design engineering; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Hardware; Integrated circuits; on-chip communication; Protocols; randomized arbitration; Resource management; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Switches; Switching, multiplexing, switched capacity circuits; System-on-a-chip; System-on-Chip (SoC); Traffic engineering; Traffic flow; Very large scale integration; Performance evaluation; High performance; Bus architecture; on-chip communication; ran domized arbitration; System-on-Chip (SoC); Transmission protocol; Resource sharing; System on a chip; Bus(channel); Implementation; Time division multiple access; Interconnection; Integrated circuit; Subsystem; Selector switch
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2006.878210

On-chip communication architectures play an important role in determining the overall performance of System-on-Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In particular, the resource sharing mechanism of the communication architecture, which determines how the often-conflicting requirements of different components are served, is of utmost importance. Conventional SoC architectures typically employ priority or time-division multiple-access (TDMA)-based communication architectures. However, these techniques are often inadequate. In the former, low-priority components may suffer from starvation, while in the latter, depending on the request profile, high-priority traffic may be subject to large latencies. This paper presents LOTTERYBUS, a high-performance SoC communication architecture based on new randomized on-chip communication protocols that addresses the shortcomings mentioned above. LOTTERYBUS provides each SoC component with a flexible, proportional, and probabilistically guaranteed share of the on-chip communication bandwidth. We present two variants of LOTTERYBUS. In the first variant, its architectural parameters are statically configured, leading to relatively low hardware overhead and design complexity. In the second variant, these parameters are allowed to vary dynamically, enabling more sophisticated use of LOTTERYBUS, at additional hardware cost. We have performed experiments to investigate the performance of LOTTERYBUS across a range of communication traffic characteristics. We have used LOTTERYBUS in designing a 4times4 ATM switch subsystem, and have compared its performance with conventional architectures. The results show that LOTTERYBUS provides fine-grained control over bandwidth allocation, and also provides significant reduction in average transaction latencies (up to 85%) compared to conventional architectures. Hardware implementations using a commercial 0.15-mum cell-based library indicate that the advantages provided by LOTTERYBUS are accompanied by modest hardware overheads compared to conventional architectures