APA (7th ed.) Citation

Lahiri, K., Raghunathan, A., & Lakshminarayana, G. (2006). The LOTTERYBUS on-chip communication architecture. IEEE transactions on very large scale integration (VLSI) systems, 14(6), 596-608. https://doi.org/10.1109/TVLSI.2006.878210

Chicago Style (17th ed.) Citation

Lahiri, K., A. Raghunathan, and G. Lakshminarayana. "The LOTTERYBUS On-chip Communication Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 6 (2006): 596-608. https://doi.org/10.1109/TVLSI.2006.878210.

MLA (9th ed.) Citation

Lahiri, K., et al. "The LOTTERYBUS On-chip Communication Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 6, 2006, pp. 596-608, https://doi.org/10.1109/TVLSI.2006.878210.