LRU-WSR: integration of LRU and writes sequence reordering for flash memory

• Published in: IEEE transactions on consumer electronics Vol. 54; no. 3; pp. 1215 - 1223
• Main Authors: Jung, Hoyoung, Shim, Hyoki, Park, Sungmin, Kang, Sooyong, Cha, Jaehyuk
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Asymmetry; buffer replacement; Buffer storage; Buffers; Cache storage; Degradation; Delay; Electric shock; Electronics; Energy consumption; Flash memory; Flash memory (computers); Hard disks; Mobile communication systems; Policies; Read-write memory; storage system; Writing
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2008.4637609

Most mobile devices are equipped with a NAND flash memory even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: write/erase operations are much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. However, existing LRU buffer replacement algorithm cannot deal with the above problem. This paper proposes the LRU-WSR buffer replacement algorithm that enhances LRU by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhanced LRU-WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The experimental results show that the LRU-WSR outperforms other algorithms including LRU, CF-LRU, and FAB 1 .