Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

• Published in: Proceedings of the IEEE Vol. 96; no. 2; pp. 343 - 365
• Main Authors: Calhoun, Benton H., Cao, Yu, Li, Xin, Mai, Ken, Pileggi, Lawrence T., Rutenbar, Rob A., Shepard, Kenneth L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Circuit synthesis; Clock distribution; Clocks; CMOS digital integrated circuits; complementary metal-oxide-semiconductor (CMOS); Construction; Design engineering; device scaling; Devices; Digital circuits; Integrated circuit interconnections; lithography; logic; Logic circuits; manufacturability; Mathematical models; memory; MOS devices; Nanocomposites; Nanomaterials; Nanoscale devices; Nanostructure; optimization; Power distribution; Power system interconnection; regular circuit fabrics; statistical variability; yield; memory; complementary metal-oxide-semiconductor (CMOS); statistical variability; device scaling; digital circuits; lithography; optimization; yield; power distribution; regular circuit fabrics; Clock distribution; logic; manufacturability
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2007.911072

Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.