On the Reliability of Majority Gates Full Adders

• Published in: IEEE transactions on nanotechnology Vol. 7; no. 1; pp. 56 - 67
• Main Authors: Ibrahim, W., Beiu, V., Sulieman, M.H.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Applied sciences; Birth disorders; Circuit properties; CMOS technology; Design engineering; Design. Technologies. Operation analysis. Testing; Digital arithmetic; Digital circuits; Digital signal processors; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Electronics industry; Energy consumption; Exact sciences and technology; Extrapolation; Full adders; Gates; Integrated circuits; Integrated circuits by function (including memories and processors); majority gates; Mathematical analysis; Molecular electronics, nanoelectronics; Nanocomposites; Nanomaterials; Nanostructure; Probability; probability of failure; probability transfer matrix; reliability; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solid state circuits; Transfer matrix; Arithmetic circuit; Full adders; probability transfer matrix; Adder; Failures; Nanoelectronics; Power consumption; probability of failure; Integrated circuit; Transfer matrix method; Reliability; majority gates
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2007.915203

This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into different parameters that affect the reliability of FAs. The probability transfer matrix method is used to exactly calculate the reliability of the FAs under investigation. All simulation results show that majority gates FAs are more robust than a standard XOR-based FA. They also show how different gates affect the FAs' reliabilities and are extrapolated to give reliability estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).