FPGA-Based Digital Pulsewidth Modulator With Time Resolution Under 2 ns

• Published in: IEEE transactions on power electronics Vol. 23; no. 6; pp. 3135 - 3141
• Main Authors: Huerta, S.C., de Castro, A., Garcia, O., Cobos, J.A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Blocking; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Delay; Digital; Digital circuits; Digital control; Digital electronics; Digital modulation; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electrical machines; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Field programmable gate arrays; field-programmable gate arrays (FPGAs); Frequencies; Linearity; Modulation; Modulators; Pulse modulation; Pulse width modulation; Pulse width modulation converters; pulsewidth modulation (PWM); Regulation and control; Signal convertors; signal resolution; Space vector pulse width modulation; Synchronous; Digital control; pulsewidth modulation (PWM); signal resolution; field-programmable gate arrays (FPGAs); Pulse width; Modulator; Field programmable gate array; Experimental study; Clock; Implementation; Time resolution; Delay lock loops; Pulse duration modulation; Cost lowering
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2008.2005370

This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.