Carrier Transport in High-Mobility III-V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications
DC and high-frequency device characteristics of In 0.7 Ga 0.3 As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I on ) gam of 20% is observe...
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Published in | IEEE electron device letters Vol. 29; no. 10; pp. 1094 - 1097 |
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Main Authors | , , , , , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.10.2008
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | DC and high-frequency device characteristics of In 0.7 Ga 0.3 As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I on ) gam of 20% is observed in the In 0.7 Ga 0.3 As QWFET over the strained Si nMOSFET at (V g - V t ) = 0.3 V, V ds = 0.5 V, and matched I off , despite higher external resistance and large gate-to-channel thickness. To understand the gain in I on , the effective carrier velocities (v eff ) near the source-end are extracted and it is observed that at constant (V g - V t ) = 0.3 V and V ds = 0.5 V, the v eff of In 0.7 Ga 0.3 As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of v eff and charge density (n s ), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In 0.7 Ga 0.3 As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher v eff will result in more than 80% I on increase over strained Si nMOSFETs at V ds = 0.5 V, (V g - V t ) = 0.3 V, and matched I off , thus showing promise for future high-speed and low-power logic applications. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2008.2002945 |