A novel all-binary motion estimation (ABME) with optimized hardware architectures

• Published in: IEEE transactions on circuits and systems for video technology Vol. 12; no. 8; pp. 700 - 712
• Main Authors: Luo, Jeng-Hung, Wang, Chung-Neng, Chiang, Tihao
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; Bandwidth; Bit rate; Circuit design; Circuit synthesis; Coding; Computational complexity; Computer architecture; Embedded system; Embedded systems; Hardware; Motion estimation; Parallel architectures; Processors; Representations; Studies; Systolic arrays
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2002.800859

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.