Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

• Published in: IEEE electron device letters Vol. 27; no. 9; pp. 759 - 761
• Main Authors: PARK, Ki-Heung, HAN, Kyoung-Rok, YOUNG MIN KIM, LEE, Jong-Ho
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Capacitance; Corners; Delay effects; Design. Technologies. Operation analysis. Testing; Devices; Doping profiles; DRAM; Dynamic random access memory; Electrodes; Electronics; Exact sciences and technology; gate-induced drain leakage (GIDL); Gates; Integrated circuits; Integrated circuits by function (including memories and processors); MOSFET circuits; MOSFETs; Nanoscale devices; Random access memory; recess channel (RC); Recesses; saddle MOSFET; Saddles; Scalability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shape; side-gate; Simulation; Threshold voltage; Transistors; Voltage threshold; High performance; MOSFET; Scalability; Random access memory; gate-induced drain leakage (GIDL); side-gate; saddle MOSFET; recess channel (RC); Integrated circuit; Capacitance; Leakage current; Delay time; DRAM; Dynamic random access memory
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.880833

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has ~ 21% lower gate capacitance and lower I off by two orders of magnitude than a conventional saddle device under nearly the same I on . In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time (CV/I) by ~ 30% than the conventional recess channel device while keeping nearly the same I off