Enhancement of Data Retention Time for 512-Mb DRAMs Using High-Pressure Deuterium Annealing

• Published in: IEEE transactions on electron devices Vol. 55; no. 12; pp. 3599 - 3601
• Main Authors: Chang, Hyo Sik, Hwang, Hyunsang
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Annealing; Applied sciences; Carriers; Design. Technologies. Operation analysis. Testing; Deuterium; Deuterium annealing; Devices; DRAM chips; Electronics; Exact sciences and technology; hot carrier; Hot carriers; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; passivation; retention time; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Three dimensional; Transistors; Trenches; Annealing; Trench technology; Random access memory; transistors; Retention factor; Transistor; Insulation technology; retention time; Integrated circuit; Hot carrier; Leakage current; Deuterium annealing; Reliability; Dynamic random access memory; Passivation
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2008.2006536

We have investigated the effect of high-pressure deuterium annealing (HPDA) for retention time improvement of 512-Mb dynamic random access memories with 3D cell transistors. Compared with a control sample annealed in a conventional forming gas (4% H 2 /N 2 ), additional annealing in a high-pressure deuterium ambient (100% D 2 ) at 400degC for 30 min improved the data retention time. This improvement can be explained by the decrease of junction leakage currents due to D 2 incorporation at the SiO 2 /Si interface near trench isolation region. In addition, HPDA introduced during postmetal anneal exhibited improved hot carrier reliability.