4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses
This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO inter...
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Published in | Materials Vol. 17; no. 8; p. 1908 |
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Main Authors | , , , , , |
Format | Journal Article |
Language | English |
Published |
Switzerland
MDPI AG
01.04.2024
|
Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO
interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔV
and ΔV
variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔV
and ΔV
, while HTRB showed only a 4% variation in both ΔV
and ΔV
. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1996-1944 1996-1944 |
DOI: | 10.3390/ma17081908 |