Improved bipolar transistor performance in a VLSI CMOS process

Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forwar...

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Bibliographic Details
Published inIEEE electron device letters Vol. 4; no. 8; pp. 294 - 296
Main Authors Yue, C.S., Huang, C.C., Schrankler, J.W., Pu, N.F., Kirchner, G.D., Rahn, C.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.08.1983
Institute of Electrical and Electronics Engineers
Subjects
Annealing
Applied sciences
Bipolar transistors
Boron
CMOS process
CMOS technology
Electronics
Epitaxial growth
Exact sciences and technology
Geometry
Implants
Photonic band gap
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
Very large scale integration
Operation study
Transistor
VLSI circuit
Complementary MOS technology
Technology
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Summary:Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector-emitter breakdown voltage can be achieved by this process. n-p-n transistors with β f = 100, BV CE0 = 9.0 V, and BV CB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/EDL.1983.25738