High-Performance Nanowire TFTs With Metal-Induced Lateral Crystallized Poly-Si Channels

High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-sc...

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Bibliographic Details
Published inIEEE electron device letters Vol. 29; no. 5; pp. 474 - 476
Main Authors Chang, Chia-Wen, Chen, Szu-Fen, Chang, Che-Lun, Deng, Chih-Kang, Huang, Jiun-Jia, Lei, Tan-Fu
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.05.2008
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.
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ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2008.920977