Improving speed of tunnel FETs logic circuits

• Published in: Electronics letters Vol. 51; no. 21; pp. 1702 - 1704
• Main Authors: Avedillo, M.J, Núñez, J
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 08.10.2015
• Subjects: adders; asymmetric conduction; Asymmetry; bootstrap circuits; bootstrapping problem; carry logic; Circuits; CMOS; CMOS integrated circuits; CMOS technology; complementary gate topology; Delay; delay degradation; digital tunnel FET circuits; field effect transistors; logic circuits; ripple carry adders; Ripples; Semiconductor devices; Semiconductor technology; speed improvements; sustained noise voltage pulses; Transistors; tunnel FET logic circuits; tunnel transistors; Tunnels (transportation); word length 8 bit; tunnel transistors; complementary gate topology; bootstrapping problem; word length 8 bit; ripple carry adders; speed improvements; digital tunnel FET circuits; carry logic; bootstrap circuits; adders; asymmetric conduction; field effect transistors; CMOS technology; delay degradation; sustained noise voltage pulses; CMOS integrated circuits; logic circuits; tunnel FET logic circuits
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2015.2416

Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.