Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device si...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 49; no. 7; pp. 1227 - 1231
Main Authors Chang-Hoon Choi, Chidambaram, P.R., Khamankar, R., Machala, C.F., Zhiping Yu, Dutton, R.W.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.07.2002
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Capacitance
Computer simulation
Corners
Depletion
Devices
Dopants
Gates
Metal oxide semiconductors
MOSFETs
Potential drop
Semiconductor device modeling
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Summary:Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2002.1013280