Simulink Behavioral Modeling of a 10-bit Pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers t...

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Bibliographic Details
Published inInternational journal of automation and computing Vol. 10; no. 2; pp. 134 - 142
Main Authors Barra, Samir, Kouda, Souhil, Dendouga, Abdelghani, Bouguechal, N. E.
Format Journal Article
LanguageEnglish
Published Berlin/Heidelberg Springer-Verlag 01.04.2013
Springer Nature B.V
Subjects
Accuracy
ADC
Amplification
Analog to digital converters
Bandwidths
Basic converters
Behavior
CAE) and Design
Computer Applications
Computer-Aided Engineering (CAD
Control
Data converters
Engineering
Error correction & detection
Matlab
Mechatronics
Operational amplifiers
Robotics
Signal processing
Simulation
Simulink环境
Slew rate
White noise
数据转换器
流水线
电气性能
行为建模
行为模拟
Behavioral modeling
sample and hold (S/H)
pipelined ADC
analog to digital converters (ADCs)
multiple digital to analog converter (MDAC)
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Summary:The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.
Bibliography:The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.
Behavioral modeling； analog to digital converters （ADCs）； pipelined ADC； multiple digital to analog converter （MDAC）； sample and hold （S/H）
11-5350/TP
ISSN:1476-8186
2153-182X
1751-8520
2153-1838
DOI:10.1007/s11633-013-0706-0