Fast Construction of SAH BVHs on the Intel Many Integrated Core (MIC) Architecture

• Published in: IEEE transactions on visualization and computer graphics Vol. 18; no. 1; pp. 47 - 57
• Main Author: Wald, I.
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.01.2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aggregates; Architecture; Arrays; Bounding volume hierarchies (BVHs); Construction; Footprints; Hierarchies; Instruction sets; Intel MIC architecture; Kernel; Kernels; Layout; Merging; Optimization; parallel BVH construction; Registers; Studies; Surface area; surface area heuristic (SAH)
• ISSN: 1077-2626; 1941-0506
• DOI: 10.1109/TVCG.2010.251

We investigate how to efficiently build bounding volume hierarchies (BVHs) with surface area heuristic (SAH) on the Intel Many Integrated Core (MIC) Architecture. To achieve maximum performance, we use four key concepts: progressive 10-bit quantization to reduce cache footprint with negligible loss in BVH quality; an AoSoA data layout that allows efficient streaming and SIMD processing; high-performance SIMD kernels for binning and partitioning; and a parallelization framework with several build-specific optimizations. The resulting system is more than an order of magnitude faster than today's high-end GPU builders for comparable BVHs; it is usually faster even than spatial median builders; it can build SAH BVHs almost as fast as existing GPUs and CPUs- and CPU-based approaches can build regular grids; and in aggregate "build+render" performance is significantly faster than the best published numbers for either of these systems, be it CPU or GPU, BVH, kd-tree, or grid.