Power Management of Datacenter Workloads Using Per-Core Power Gating

• Published in: IEEE computer architecture letters Vol. 8; no. 2; pp. 48 - 51
• Main Authors: Leverich, Jacob, Monchiero, Matteo, Talwar, Vanish, Ranganathan, Parthasarathy, Kozyrakis, Christos
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application software; Costs; Dynamic voltage scaling; Dynamics; Electric potential; Energy conservation; Energy consumption; Energy management; Energy-aware systems; Frequency; Gating and risering; integration and modeling; Jacobian matrices; Leakage; Management; Microprocessors; Multicore processing; Power management; Power supplies; Processors; System architectures; Testing; Voltage; Workload
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/L-CA.2009.46

While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.