Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

• Published in: IEEE transactions on multi-scale computing systems Vol. 2; no. 1; pp. 49 - 60
• Main Authors: Prenat, Guillaume, Garello, Kevin, Langer, Juergen, Ocker, Berthold, Cyrille, Marie-Claire, Gambardella, Pietro, Tahoori, Mehdi, Gaudin, Gilles, Jabeur, Kotb, Vanhauwaert, Pierre, Pendina, Gregory Di, Oboril, Fabian, Bishnoi, Rajendra, Ebrahimi, Mojtaba, Lamard, Nathalie, Boulle, Olivier
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2016
• Subjects: cache; Current density; design flow; Engineering Sciences; Gem5; leon; Magnetic separation; Magnetic tunneling; Magnetization; MRAM; multicore; NVFF; NVSIM; processor; SOT; Spin Orbit Torque; Switches; Torque; Writing; spin orbit torque; cache; design flow; MRAM; Gem5; SOT; leon; NVSIM; NVFF; processor; multicore
• ISSN: 2332-7766; 2332-7766
• DOI: 10.1109/TMSCS.2015.2509963

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of "read disturb", thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.