Low-resistance ultrashallow extension formed by optimized flash lamp annealing

• Published in: IEEE transactions on semiconductor manufacturing Vol. 16; no. 3; pp. 417 - 422
• Main Authors: Ito, T., Suguro, K., Tamura, M., Taniguchi, T., Ushiku, Y., Iinuma, T., Itani, T., Yoshioka, M., Owada, T., Imaoka, Y., Murayama, H., Kusuda, T.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.08.2003; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Annealing; Applied sciences; Electrical resistivity; Electronics; Exact sciences and technology; Flash lamps; Heating; Implantation; Impurities; Indium tin oxide; Interfaces; Lamps; Leakage; Microelectronic fabrication (materials and surfaces technology); MOSFETs; Optimization; Optimization methods; Rapid thermal annealing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Slip; Stress; Temperature; Thermal resistance; Microelectronic fabrication; Ion implantation; Annealing; Sheet resistivity; Doping; Cracking; Electronic flash lamp; Leakage current; Optimization; Shallow junction
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2003.815621

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.