Selectively doped heterostructure frequency dividers

• Published in: IEEE electron device letters Vol. 4; no. 10; pp. 377 - 379
• Main Authors: Kiehl, R.A., Feuer, M.D., Hendel, R.H., Hwang, J.C.M., Keramidas, V.G., Allyn, C.L., Dingle, R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.1983; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit properties; Counting circuits; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Electrons; Exact sciences and technology; FETs; Frequency conversion; Gallium arsenide; Heterojunctions; Logic circuits; Logic gates; Optical buffering; Power dissipation; Digital counter; Gallium Arsenides; Field effect transistor; Aluminium Gallium Arsenides; Microelectronic fabrication; Lithography; Epitaxy; Frequency divider; Molecular beam; Fast circuit; Heterojunction
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/EDL.1983.25770

The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having 1-µm gate lengths and 4-µm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al .3 Ga .7 As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.