An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning

• Published in: IEEE access Vol. 8; pp. 50911 - 50920
• Main Authors: Huang, Zhipeng, Lin, Zhifeng, Zhu, Ziran, Chen, Jianli
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Aspect ratio; Clustering algorithms; Cost function; Estimation; excessive violation function; feasible solution strategy; fixed-outline; Floorplanning; Floorplans; Heuristic algorithms; Modules; Optimization; Penalty function; Perturbation methods; Simulated annealing; simulated annealing algorithm
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2020.2980135

In addition to wirelength and area, modern floorplans need to consider various constraints such as fixed-outline. To handle the fixed-outline floorplanning optimization problem efficiently, we propose an improved simulated annealing (SA) algorithm, which optimizes the area, the total wirelength, and the prescribed outline constraints at the same time. In order to enhance the effectiveness of SA algorithm, we propose a novel feasible solution strategy which ensures that viable solution would be found at all times. Moreover, we propose a new penalty function to better solve the prescribed outline constraint. It consists of a violation area function to prevent modules from moving to the prescribed outline, and an excessive violation function to enable the modules to move close to the optimal positions. Experimental results show that the proposed algorithm is effective and efficient to obtain a fixed-outline floorplan, and achieves a 100% success rate on each benchmark in different aspect ratios.