Sensitivity Analysis of Strictly Periodic Tasks in Multi-Core Real-Time Systems

• Published in: IEEE access Vol. 7; pp. 135005 - 135022
• Main Authors: Chen, Jinchao, Du, Chenglie, Han, Pengcheng, Zhang, Yong
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Design modifications; Game theory; Microprocessors; multi-core real-time system; Parameter identification; Parameter modification; Parameter sensitivity; Processor scheduling; Real time; Real-time systems; schedulability analysis; Scheduling; scheduling algorithm; Sensitivity analysis; strictly periodic task; Task analysis; Timing
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2019.2941958

In the design phase of real-time systems, it cannot be expected that the timing attributes of all tasks are completely specified and never changed. The increased computation times or shortened periods in a schedulable system often cause deadlines to be missed. In such situations, sensitivity analysis is an effective approach to provide quantitative indications for the design modification, by identifying the borderlines on parameter variations while keeping the systems schedulable. In this paper, we propose a new approach to analyze the sensitivity of the timing parameters of tasks with strict periods in multi-core real-time systems. We first analyze a schedulability condition to determine whether a task is schedulable on a given processor without changing the start times of the existing tasks. Then, following a game theory analogy, we design recursive algorithms to compute the permissible changes in the task timing parameters, by allowing each task to optimize its own start time and processor allocation. Finally, we conduct experiments with randomly generated tasks to show that our approach is more efficient than the existing solutions to solve the sensitivity problem. The proposed approach has a wide range of applications, only guiding the design of multi-core systems, but also improving the robustness of a design subject to future changes.