Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration

• Published in: IEEE access Vol. 9; pp. 38043 - 38061
• Main Authors: Mohan, Charanraj, Camunas-Mesa, L. A., De La Rosa, Jose M., Vianello, Elisa, Serrano-Gotarredona, Teresa, Linares-Barranco, Bernabe
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Calibration; Circuits; CMOS; Inference; Learning; Logic gates; low-power inference; Memory devices; memristive crossbar; Memristors; nano-synapse; Neuromorphic; Neuromorphics; Neurons; offset calibration; Pattern recognition; Power amplifiers; Power management; Pulse amplitude; Random access memory; Synapses; System-on-chip; Template matching
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3063437

Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability and low power operation. After learning, however, a read inference can be made low-power by applying very small amplitude read pulses, which require much smaller driving currents per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately, applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome this, we propose finely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4×4 proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a 4×4 1T1R synapse crossbar was designed and fabricated in the CEA-LETI MAD200 technology, which uses monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the post-synaptic circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization, template matching, and pattern recognition using STDP learning, and to demonstrate the use of on-chip offset-calibrated low-power amplifiers. According to our experiments, the minimum possible inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some suggestions for future work in this direction.