Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time ( T ret ). For high device scalability and low program voltage ( V P ), lengths of the...

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Bibliographic Details
Published inIEEE open journal of nanotechnology Vol. 1; pp. 163 - 169
Main Authors Kim, Hyangwoo, Cho, Hyeonsu, Kong, Byoung Don, Kim, Jin-Woo, Meyyappan, Meyya, Baek, Chang-Ki
Format Journal Article
LanguageEnglish
Published New York IEEE 2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Anodes
Arrays
Carrier injection
Depletion
Doping
DRAM Chips
Electric potential
Impact ionization
Mathematical model
memory architecture
Operating temperature
Power demand
Random access memory
semiconductor device modeling
semiconductor devices
thyristor applications
Thyristors
Volt-ampere characteristics
Voltage
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Summary:Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time ( T ret ). For high device scalability and low program voltage ( V P ), lengths of the storage regions are determined by the sum of depletion widths of N- and P-storage regions. When doping concentrations of two storage regions are equal to each other at 10 18 cm −3 , 2-T TRAM exhibits the longest T ret of 100 ms and the lowest impact ionization of the device can suppress various reliability issues such as hot carrier injection and junction degradation. Although T ret of 2-T TRAM can be reduced from 100 ms to 1.5 ms due to decreased read voltage with operating temperature rising from 300 K to 360 K, T ret can be further improved to >10 s by applying standby voltage ( V standby ). The effective way to set minimum V standby is presented using the I A - V A characteristics with 1000-s fall time. Moreover, the optimal V standby is set to 0.60 V by considering disturbance in array operation. Consequently, the proposed design and operation guidelines can provide a pathway to realize nanoscale 2-T TRAM for capacitor-less 4F 2 1T DRAM technology.
ISSN:2644-1292
2644-1292
DOI:10.1109/OJNANO.2020.3042804