Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review
Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the adva...
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Published in | IEEE access Vol. 10; p. 1 |
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Main Authors | , , , , , , , |
Format | Journal Article |
Language | English |
Published |
Piscataway
IEEE
2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated. |
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ISSN: | 2169-3536 2169-3536 |
DOI: | 10.1109/ACCESS.2022.3217919 |