An Efficient Algorithm and Hardware Architecture for Maximum-Likelihood Based Carrier Frequency Offset Estimation in MIMO Systems

• Published in: IEEE access Vol. 6; pp. 50105 - 50116
• Main Authors: Zhou, Mingda, Feng, Zhe, Liu, Youjian, Huang, Xinming
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Carrier frequencies; Carrier frequency offset; Computer architecture; Cramer-Rao bounds; Field programmable gate arrays; FPGA; Frame structures; Frequency estimation; Hardware; hardware architecture; Lower bounds; Maximum likelihood estimation; maximum-likelihood; MIMO; MIMO communication; OFDM; Oscillators; Pipelining (computers); Signal to noise ratio; Wireless communication systems; Wireless communications
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2018.2869114

Carrier frequency offset (CFO), which is often caused by the mismatch between the local oscillators in transmitter and receiver, limits the performance of multiple-input multiple-output (MIMO) wireless communication systems. This paper presents a maximum-likelihood-based CFO estimation algorithm for MIMO systems and its efficient hardware design. The proposed algorithm can accurately estimate the CFO, especially at high signal-to-noise ratio. Moreover, the Cramer-Rao lower bound of the proposed method is derived as a performance guideline. In terms of hardware implementation, an efficient pipeline architecture is presented in detail, showing that the architecture only occupies minimal hardware resources so that it can be fitted into a small field-programmable gate array. The proposed architecture can be reconfigured according to different pilot lengths, making it flexible to various frame structures.