Interlayer coupling effect on the performance of monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness

• Published in: Japanese Journal of Applied Physics Vol. 56; no. 4S; pp. 4 - 04CC02
• Main Authors: Hattori, Junichi, Fukuda, Koichi, Irisawa, Toshifumi, Ota, Hiroyuki, Maeda, Tatsuro
• Format: Journal Article
• Language: English
• Published: The Japan Society of Applied Physics 01.04.2017
• Subjects: Coupling; Delay; Dielectrics; Field effect transistors; Interlayers; Inverters; Semiconductor devices; Voltage
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/JJAP.56.04CC02

We study the interlayer coupling in monolithic three-dimensional (3D) inverters and investigate its effect on the performance of 3D inverters using technology computer-aided design simulation. The interlayer coupling in 3D inverters consisting of silicon-on-insulator metal-oxide-semiconductor field-effect transistors (FETs) improves the current driving capability of the top FETs. Owing to this improvement, 3D inverters have a smaller intrinsic delay than the corresponding two-dimensional (2D) inverters although the switching energies of 3D and 2D inverters are comparable to each other. We analyze the relationship of such interlayer coupling effects with the interlayer dielectric (ILD) thickness and find that there exists an appropriate ILD thickness in terms of various aspects of the performance such as speed, energy efficiency, and both. It is also found that decreasing the power supply voltage enhances the interlayer coupling effects. In addition, we reveal that the interlayer coupling in 3D inverters is strongly dependent on the original structure of the constituent FETs.