An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability

This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigur...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 7; pp. 1235 - 1244
Main Authors Yang, Chi-Heng, Lin, Yi-Min, Chang, Hsie-Chia, Lee, Chen-Yi
Format Journal Article
LanguageEnglish
Published IEEE 01.07.2015
Subjects
Ash
Bose-Chaudhuri-Hocquenghem (BCH) codes
Codecs
Complexity theory
Computer architecture
encoder
error correcting codes (ECC)
Generators
Hardware
NAND flash
Polynomials
syndrome
Bose–Chaudhuri–Hocquenghem (BCH) codes
syndrome
encoder
error correcting codes (ECC)
NAND flash
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Summary:This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1-24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60-84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2338309