Fabrication of wire-MOSFETs on silicon-on-insulator substrate
This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors bel...
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Published in | Microelectronic engineering Vol. 61; pp. 613 - 618 |
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Main Authors | , , , , , , , |
Format | Journal Article Conference Proceeding |
Language | English |
Published |
Amsterdam
Elsevier B.V
01.07.2002
Elsevier Science |
Subjects | |
Online Access | Get full text |
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Summary: | This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. |
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Bibliography: | SourceType-Scholarly Journals-2 ObjectType-Feature-2 ObjectType-Conference Paper-1 content type line 23 SourceType-Conference Papers & Proceedings-1 ObjectType-Article-3 |
ISSN: | 0167-9317 1873-5568 1873-5568 |
DOI: | 10.1016/S0167-9317(02)00465-3 |