Fabrication of wire-MOSFETs on silicon-on-insulator substrate

• Published in: Microelectronic engineering Vol. 61; pp. 613 - 618
• Main Authors: Heuser, M., Baus, M., Hadam, B., Winkler, O., Spangenberg, B., Granzner, R., Lemme, M., Kurz, H.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Amsterdam Elsevier B.V 01.07.2002; Elsevier Science
• Subjects: Applied sciences; Double gate; Electronics; Exact sciences and technology; Fully depleted; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon-on-insulator (SOI); Transistors; Triple-sided gate structure; Wire MOSFET; Silicon-on-insulator (SOI); Fully depleted; Wire MOSFET; Double gate; Triple-sided gate structure; Silicon on insulator technology; MOSFET; Potential barrier; Transistor channel; n type semiconductor; Short channel; Punch through effect
• ISSN: 0167-9317; 1873-5568; 1873-5568
• DOI: 10.1016/S0167-9317(02)00465-3

This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly.